 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| (Preliminary)PLL500-15/16 Low Phase Noise VCXO (1MHz to 18MHz) FEATURES * * * * * * * * * * * VCXO with Divider Selection (DIVSEL) input pin * PLL500-15: /8, /16 * PLL500-16: /2, /4 VCXO output for the 1MHz to 18MHz range 16MHz to 36MHz fundamental crystal input. Low phase noise (-130 dBc @ 10kHz offset using a 35.328MHz crystal). CMOS output with OE tri-state control. Integrated high linearity variable capacitors. 12mA drive capability at TTL output. 150 ppm pull range, max 5% linearity. Low jitter (RMS): 2.5ps period jitter. 2.5V to 3.3V operation. Available in 8-Pin SOIC, 6-pin SOT23 GREEN/ RoHS compliant packages, or DIE. PIN CONFIGURATION XIN VCON DIVSEL^ GND 1 2 3 4 8 7 6 5 XOUT OE^ VDD CLK SOIC-8 PLL500-15/16 P500-15/16 1 2 3 6 5 4 XOUT VDD CLK XIN VCON GND DESCRIPTION The PLL500-15/16 is a low cost, high performance and low phase noise VCXO for the 1.0MHz to 18MHz range, providing less than -130dBc at 10kHz offset when using a 35.328MHz crystal. The very low jitter (2.5 ps RMS period jitter) makes this chip ideal for applications requiring voltage controlled frequency sources. Input crystal can range from 16MHz to 36MHz (fundamental resonant mode). SOT23-6* ^: Denotes internal Pull-up *: SOT package offers single divider option only DIVIDER SELECTION LOGIC LEVELS Part # PLL500-15 PLL500-16 DivSel State 1 (Default) 0 1 (Default) 0 Operation /16 /8 /4 /2 BLOCK DIAGRAM DIVSEL XIN VCXO XOUT VCON Varicap Selectable Divider CLK 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/12/06 Page 1 (Preliminary)PLL500-15/16 Low Phase Noise VCXO (1MHz to 18MHz) DIE PAD LAYOUT DIE SPECIFICATIONS Name Value 32 mil (812,986) 8 1 XIN XOUT OE^ 7 39 mil 2 VCON VDD 6 Size Reverse side Pad dimensions Thickness 39 x 32 mil GND 80 micron x 80 micron 10 mil 3 DIVSEL^ 4 GND CLK 5 DIE ID: PLL500-15: C500A A1111-12 PLL500-16: C500A A1111-11 Y X (0,0) Note: ^ denotes internal pull up PACKAGE PIN and DIE PAD ASSIGNMENT Pin# Name XIN VCON DIVSEL GND CLK VDD OE XOUT Die Pad Position X (m) 94.183 94.157 94.183 94.193 715.472 715.307 715.472 476.906 SOP-8 1 2 3 4 5 6 7 8 SOT23-6 6 5 4 3 2 1 Y (m) 768.599 605.029 331.756 140.379 203.866 455.726 626.716 888.881 Type I P I P O P I I Crystal input pin. Description Frequency Control Voltage input pin. Divider Selection input pin. Default Logic 1 for SOT23 package. See Divider Selection Logic Levels table on Page 1. Ground pin. Output clock pin. VDD power supply pin. Output Enable input pin. Disables the output when low. Internal pull-up enables output by default if pin is not connected to low. Default "Enabled" (Logic 1) for SOT23 package. Crystal output pin. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/12/06 Page 2 (Preliminary)PLL500-15/16 Low Phase Noise VCXO (1MHz to 18MHz) ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model SYMBOL VDD VI VO TS TA TJ MIN. -0.5 -0.5 -65 -40 MAX. 4.6 VDD+0.5 VDD+0.5 150 85 125 260 2 UNITS V V V C C C C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. 2. AC Electrical Specifications PARAMETERS Input Crystal Frequency Output Clock Rise/Fall Time Output Clock Duty Cycle 0.8V ~ 2.0V with 10 pF load 0.3V ~ 3.0V with 15 pF load Measured @ 1.4V 45 SYMBOL CONDITIONS MIN. 16 TYP. 1.15 3.7 50 MAX. 36 UNITS MHz ns 55 % 3. Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time * VCXO Tuning Range CLK output pullability VCXO Tuning Characteristic Pull range linearity Power Supply Rejection VCON pin input impedance VCON modulation BW PWSRR SYMBOL TVCXOSTB CONDITIONS From power valid XTAL C0/C1 < 250 0V VCON 3.3V VCON=1.65V, 1.65V MIN. TYP. 300 MAX. 10 UNITS ms ppm ppm ppm/V % ppm k kHz 150 100 5 Frequency change with VDD varied +/- 10% 0V VCON 3.3V, -3dB -1 2000 45 +1 Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/12/06 Page 3 (Preliminary)PLL500-15/16 Low Phase Noise VCXO (1MHz to 18MHz) 4. Jitter and Phase Noise Specifications PARAMETERS RMS Period Jitter (1 sigma - 1000 samples) Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier CONDITIONS With capacitive decoupling between VDD and GND. 18MHz @100Hz offset 18MHz @1kHz offset 18MHz @10kHz offset 18MHz @100kHz offset 18MHz @1MHz offset MIN. TYP. 2.5 -75 -105 -125 -133 -140 MAX. UNITS ps dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 5. DC Specifications PARAMETERS Supply Current, Dynamic, with Loaded Outputs Operating Voltage Output Low Voltage at CMOS level Output High Voltage at CMOS level Output drive current VCXO Control Voltage SYMBOL IDD VDD VOLC VOHC VCON CONDITIONS FXIN = 36MHz Output load of 15pF MIN. TYP. 5 MAX. 6 3.63 0.4 UNITS mA V V V 2.25 IOL = +4mA IOH = -4mA For VOL<0.4V or VOH>2.4V VDD - 0.4 8 0 9.5 VDD mA V 6. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating (VCON = 1.65V) Maximum Sustainable Drive Level Operating Drive Level C0 C0/C1 ESR SYMBOL FXIN CL (xtal) MIN. 16 TYP. 8.5 MAX. 36 200 UNITS MHz pF W W pF 50 5 250 30 RS Note: The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/12/06 Page 4 (Preliminary)PLL500-15/16 Low Phase Noise VCXO (1MHz to 18MHz) PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT) SOIC 8L Symbol A A1 A2 B C D E H L e SOT-23 6L Symbol A A1 A2 B C D E H L e Dimension in MM Min. Max. 1.05 1.35 0.05 0.15 1.00 1.20 0.30 0.50 0.08 0.20 2.80 3.00 1.50 1.70 2.60 3.00 0.35 0.55 0.95 BSC Dimension in MM Min. Max. 1.35 1.75 0.10 0.25 1.25 1.50 0.33 0.53 0.19 0.27 4.80 5.00 3.80 4.00 5.80 6.20 0.40 0.89 1.27 BSC E H D A2 A A1 e b C L E H D A2 A A1 e b C L 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/12/06 Page 5 (Preliminary)PLL500-15/16 Low Phase Noise VCXO (1MHz to 18MHz) ORDERING INFORMATION (GREEN PACKAGE COMPLIANT) For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range PLL500-XX X X X X PART NUMBER NONE= TUBE R=TAPE AND REEL NONE=NORMAL PACKAGE L=GREEN PACKAGE PACKAGE TYPE D=Die S= SOIC-8L T= SOT23-6L Part / Order Number PLL500-15DC PLL500-15SC PLL500-15SC-R PLL500-15SCL PLL500-15SCL-R PLL500-15TC PLL500-15TC-R PLL500-15TCL PLL500-15TCL-R PLL500-16DC PLL500-16SC PLL500-16SC-R PLL500-16SCL PLL500-16SCL-R PLL500-16TC PLL500-16TC-R PLL500-16TCL PLL500-16TCL-R Marking P500-15DC P500-15SC P500-15SC P500-15SCL P500-15SCL P500-15TC P500-15TC P500-15TCL P500-15TCL P500-16DC P500-16SC P500-16SC P500-16SCL P500-16SCL P500-16TC P500-16TC P500-16TCL P500-16TCL TEMPERATURE C=COMMERCIAL I=INDUSTRIAL Package Option Die (Waffle Pack) 8-Pin SOIC (Tube) 8-Pin SOIC (Tape and Reel) 8-Pin SOIC GREEN (Tube) 8-Pin SOIC GREEN (Tape and Reel) 6-Pin SOT23 (Tube) 6-Pin SOT23 (Tape and Reel) 6-Pin SOT23 GREEN (Tube) 6-Pin SOT23 GREEN (Tape and Reel) Die (Waffle Pack) 8-Pin SOIC (Tube) 8-Pin SOIC (Tape and Reel) 8-Pin SOIC GREEN (Tube) 8-Pin SOIC GREEN (Tape and Reel) 6-Pin SOT23 (Tube) 6-Pin SOT23 (Tape and Reel) 6-Pin SOT23 GREEN (Tube) 6-Pin SOT23 GREEN (Tape and Reel) PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/12/06 Page 6 |
Price & Availability of P500-16TCL
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |